1. Field of the Invention
The present invention generally relates to packaging of integrated circuit devices, and is particularly related to a thin film capacitor formed on a silicon/silicon oxide substrate interposer, which is connected to a ceramic substrate and to a method of making the same.
2. Description of the Related Art
As integrated circuit (IC) chips have increased in complexity and decreased in size, the formation of interconnections between IC chips has also greatly increased in complexity. Many devices, such as computers, use a number of separate IC chips. For example, a computer may include one or more central processing units, an arithmetic processor, various controller and memory chips, input/output interface chips, etc. Conventionally, each IC chip is mounted individually in a separate package that is connected to a printed circuit board, for example, a computer xe2x80x9cmotherboard,xe2x80x9d which provides power and signal interconnections to the mounted IC chips. However, when a device requires a large number of IC chips, individually packaging and mounting each IC chip greatly increases the printed circuit board area required to interconnect all the IC chips. Additionally, as device speed has increased, it has become more important to minimize the path lengths between IC chips, themselves, and the other electronic components connected to the IC chips.
To decrease printed circuit board space, distance between IC chips and the complexity of interconnections, many devices now use multichip modules (MCMs) that incorporate a number of IC chips into one package. Using one package reduces the distance between IC chips, thus, permitting greater device speeds. The multichip modules usually provide power and signal interconnections to the individual IC chips from an underlying ceramic substrate.
Multichip modules may be two-dimensional, that is, all the IC chips of a package are mounted on a planar substrate, or three-dimensional, where IC chips are mounted above or below a ceramic substrate, another IC chip, or an interposer. An interposer is a structure on which various electronic components and interconnections are formed and is usually located between an IC chip and a ceramic substrate, another interposer, or a printed circuit board.
As the switching speed of devices increases, it is important to provide a decoupling capacitance in close proximity to the IC chips of the multichip module. Conventionally, a discrete capacitor has been mounted on a surface of a ceramic substrate or a decoupling capacitance has been incorporated into the ceramic substrate. The former approach uses valuable real estate on the surface of the ceramic substrate and does not place the discrete capacitor in close proximity to the IC chip, while the latter approach increases the complexity of the ceramic substrate and thus, decreases yields.
In view of the foregoing and other problems and disadvantages of conventional methods, an object of the present invention is to provide an interposer having a silicon/silicon oxide substrate, on which is formed a high performance thin film dielectric capacitor that may connect an integrated circuit, e.g., IC chips or wafers, to a ceramic substrate.
Another object of the present invention is to provide a method of manufacturing an interposer having a silicon/silicon oxide substrate, on which is formed a high performance thin film dielectric capacitor, having good yield, relatively low cost and using standard IC fabrication processes.
A further object of the present invention is to provide an interposer having a silicon/silicon oxide substrate, on which is formed a thin film dielectric capacitor, to electrically decouple the signal interconnections from the power and ground interconnections, which connect to an integrated circuit.
In order to attain the above and other objects, according to an exemplary embodiment of the present invention, disclosed herein is an interposer, located between an integrated circuit having power, ground and signal connections and a ceramic substrate having power, ground and signal connections, that may include an oxide layer formed on a polished surface of a silicon substrate, a thin film dielectric capacitor formed on the oxide layer, metallized vias, each of which connects to either an upper or a lower electrode of the thin film capacitor, and vias that connect power, ground and signals between the ceramic substrate and the integrated circuit.
According to another exemplary embodiment of the present invention, the thin film capacitor may comprise platinum electrodes and a dielectric composed of high-K titanates, such as, barium zirconate titanate, barium strontium titanate, pure barium titanate, barium titanate modified with Pb, Nb, W, Ca, Mg and Zn, lead titanate, lead zirconate titanate, or polycrystalline lanthanum-modified lead zirconate titanate, or other high-K dielectric materials, such as, lead niobate and its derivatives, and lead tungstate and its derivatives.
According to another exemplary embodiment of the present invention, solder connections may connect the metallized vias of the interposer, connecting each of both electrodes of the thin film dielectric capacitor, to the integrated circuit and other vias of the interposer, conducting power, ground and signals, to the ceramic substrate.
According to another exemplary embodiment of the present invention, the interposer may be fabricated by chemical-mechanical polishing of a surface of a silicon substrate upon which is formed an oxide layer, thinning the oxidized silicon substrate by chemical-mechanical polishing of the non-polished surface of the silicon substrate, forming a thin film dielectric capacitor on the oxide layer, making vias that connect to either of the electrodes of the thin film capacitor and metallizing these vias, and forming vias that connect power, ground and signals between the ceramic substrate and the integrated circuit.
According to another exemplary embodiment of the present invention, making the vias that electrically connect to either of the electrodes of the thin film dielectric capacitor may utilize both chemical-mechanical polishing (CMP) and accurate endpoint detection.
According to another exemplary embodiment of the present invention, the dielectric of the thin film dielectric capacitor may be annealed at temperatures from about 350xc2x0 C. to about 1000xc2x0 C.
According to another exemplary embodiment of the present invention, the patterning of the thin film dielectric capacitor to form at least one capacitor may be accomplished by forming a stencil and ion milling the electrodes and the dielectric layer of the thin film dielectric capacitor.
According to another exemplary embodiment of the invention, a system using a decoupling capacitance may include a ceramic substrate having power, ground and signal connections, an integrated circuit having power, ground and signal connections, and an interposer having a thin film dielectric capacitor that is electrically coupled to the integrated circuit and vias that conduct power, ground and signals between the ceramic substrate and the integrated circuit.
Thus, the present invention overcomes the problems of the conventional methods and structures by using a high performance thin film dielectric capacitor, having low parasitic and low inductance capacitance, formed on an interposer that may be positioned between an IC chip and a ceramic substrate. One side of the interposer, on which is formed the thin film dielectric capacitor, may be connected to the ceramic substrate by vias that transfer power, ground and signals. On the other side of the interposer, an IC chip may be attached to vias connected to the thin film capacitor electrodes. In this manner, the thin film dielectric capacitor may be located in close proximity to the IC chip to provide improved decoupling to the IC chip.
The interposer may be manufactured separately and tested before incorporation into the multichip module. This is particularly important because the thin film dielectric capacitor may be one of the most likely components to be defective, due to the close spacing of the plate electrodes and the possibility of pin-hole defects or surface irregularities causing electrical shorts or leakage in the dielectric layer between the plate electrodes.